// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  isp_yuvsc12p_reg_reg_offset.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2013/3/10
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/19 14:39:14 Create file
// ******************************************************************************

#ifndef __ISP_YUVSC12P_REG_REG_OFFSET_H__
#define __ISP_YUVSC12P_REG_REG_OFFSET_H__

/* ISP_YUVSC12P_REG Base address of Module's Register */
#define SOC_ISP_YUVSC12P_REG_BASE                       (0x3000)

/******************************************************************************/
/*                      SOC ISP_YUVSC12P_REG Registers' Definitions                            */
/******************************************************************************/

#define SOC_ISP_YUVSC12P_REG_IHLEFT_REG        (SOC_ISP_YUVSC12P_REG_BASE + 0x0)   /* H first pixel. */
#define SOC_ISP_YUVSC12P_REG_IHRIGHT_REG       (SOC_ISP_YUVSC12P_REG_BASE + 0x4)   /* H Last  pixel. */
#define SOC_ISP_YUVSC12P_REG_UV_HOFFSET_REG    (SOC_ISP_YUVSC12P_REG_BASE + 0x8)   /* H Chroma phase offset. */
#define SOC_ISP_YUVSC12P_REG_IVTOP_REG         (SOC_ISP_YUVSC12P_REG_BASE + 0xC)   /* V first line. */
#define SOC_ISP_YUVSC12P_REG_IVBOTTOM_REG      (SOC_ISP_YUVSC12P_REG_BASE + 0x10)  /* V last line. */
#define SOC_ISP_YUVSC12P_REG_UV_VOFFSET_REG    (SOC_ISP_YUVSC12P_REG_BASE + 0x14)  /* V Chroma phase offset. */
#define SOC_ISP_YUVSC12P_REG_IHINC_REG         (SOC_ISP_YUVSC12P_REG_BASE + 0x18)  /* H Inc for Luma. */
#define SOC_ISP_YUVSC12P_REG_IVINC_REG         (SOC_ISP_YUVSC12P_REG_BASE + 0x1C)  /* V Inc for Luma. */
#define SOC_ISP_YUVSC12P_REG_BYPASS_REG        (SOC_ISP_YUVSC12P_REG_BASE + 0x24)  /* bypass mode. */
#define SOC_ISP_YUVSC12P_REG_FORMAT_REG        (SOC_ISP_YUVSC12P_REG_BASE + 0x28)  /* format configuration. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_Y0_0_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0x60)  /* horizontal y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_Y0_1_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0x64)  /* horizontal y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_Y0_2_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0x68)  /* horizontal y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_Y0_3_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0x6C)  /* horizontal y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_Y0_4_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0x70)  /* horizontal y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_Y0_5_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0x74)  /* horizontal y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_Y0_6_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0x78)  /* horizontal y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_Y0_7_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0x7C)  /* horizontal y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_Y1_0_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0x80)  /* horizontal y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_Y1_1_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0x84)  /* horizontal y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_Y1_2_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0x88)  /* horizontal y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_Y1_3_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0x8C)  /* horizontal y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_Y1_4_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0x90)  /* horizontal y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_Y1_5_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0x94)  /* horizontal y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_Y1_6_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0x98)  /* horizontal y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_Y1_7_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0x9C)  /* horizontal y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_Y0_0_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0xA0)  /* vertical y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_Y0_1_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0xA4)  /* vertical y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_Y0_2_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0xA8)  /* vertical y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_Y0_3_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0xAC)  /* vertical y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_Y0_4_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0xB0)  /* vertical y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_Y0_5_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0xB4)  /* vertical y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_Y0_6_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0xB8)  /* vertical y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_Y0_7_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0xBC)  /* vertical y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_Y1_0_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0xC0)  /* vertical y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_Y1_1_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0xC4)  /* vertical y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_Y1_2_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0xC8)  /* vertical y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_Y1_3_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0xCC)  /* vertical y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_Y1_4_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0xD0)  /* vertical y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_Y1_5_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0xD4)  /* vertical y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_Y1_6_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0xD8)  /* vertical y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_Y1_7_REG  (SOC_ISP_YUVSC12P_REG_BASE + 0xDC)  /* vertical y coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_UV0_0_REG (SOC_ISP_YUVSC12P_REG_BASE + 0xE0)  /* horizontal uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_UV0_1_REG (SOC_ISP_YUVSC12P_REG_BASE + 0xE4)  /* horizontal uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_UV0_2_REG (SOC_ISP_YUVSC12P_REG_BASE + 0xE8)  /* horizontal uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_UV0_3_REG (SOC_ISP_YUVSC12P_REG_BASE + 0xEC)  /* horizontal uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_UV0_4_REG (SOC_ISP_YUVSC12P_REG_BASE + 0xF0)  /* horizontal uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_UV0_5_REG (SOC_ISP_YUVSC12P_REG_BASE + 0xF4)  /* horizontal uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_UV0_6_REG (SOC_ISP_YUVSC12P_REG_BASE + 0xF8)  /* horizontal uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_UV0_7_REG (SOC_ISP_YUVSC12P_REG_BASE + 0xFC)  /* horizontal uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_UV1_0_REG (SOC_ISP_YUVSC12P_REG_BASE + 0x100) /* horizontal uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_UV1_1_REG (SOC_ISP_YUVSC12P_REG_BASE + 0x104) /* horizontal uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_UV1_2_REG (SOC_ISP_YUVSC12P_REG_BASE + 0x108) /* horizontal uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_UV1_3_REG (SOC_ISP_YUVSC12P_REG_BASE + 0x10C) /* horizontal uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_UV1_4_REG (SOC_ISP_YUVSC12P_REG_BASE + 0x110) /* horizontal uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_UV1_5_REG (SOC_ISP_YUVSC12P_REG_BASE + 0x114) /* horizontal uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_UV1_6_REG (SOC_ISP_YUVSC12P_REG_BASE + 0x118) /* horizontal uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_H_UV1_7_REG (SOC_ISP_YUVSC12P_REG_BASE + 0x11C) /* horizontal uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_UV0_0_REG (SOC_ISP_YUVSC12P_REG_BASE + 0x120) /* vertical uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_UV0_1_REG (SOC_ISP_YUVSC12P_REG_BASE + 0x124) /* vertical uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_UV0_2_REG (SOC_ISP_YUVSC12P_REG_BASE + 0x128) /* vertical uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_UV0_3_REG (SOC_ISP_YUVSC12P_REG_BASE + 0x12C) /* vertical uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_UV0_4_REG (SOC_ISP_YUVSC12P_REG_BASE + 0x130) /* vertical uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_UV0_5_REG (SOC_ISP_YUVSC12P_REG_BASE + 0x134) /* vertical uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_UV0_6_REG (SOC_ISP_YUVSC12P_REG_BASE + 0x138) /* vertical uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_UV0_7_REG (SOC_ISP_YUVSC12P_REG_BASE + 0x13C) /* vertical uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_UV1_0_REG (SOC_ISP_YUVSC12P_REG_BASE + 0x140) /* vertical uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_UV1_1_REG (SOC_ISP_YUVSC12P_REG_BASE + 0x144) /* vertical uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_UV1_2_REG (SOC_ISP_YUVSC12P_REG_BASE + 0x148) /* vertical uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_UV1_3_REG (SOC_ISP_YUVSC12P_REG_BASE + 0x14C) /* vertical uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_UV1_4_REG (SOC_ISP_YUVSC12P_REG_BASE + 0x150) /* vertical uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_UV1_5_REG (SOC_ISP_YUVSC12P_REG_BASE + 0x154) /* vertical uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_UV1_6_REG (SOC_ISP_YUVSC12P_REG_BASE + 0x158) /* vertical uv coeff table. */
#define SOC_ISP_YUVSC12P_REG_COEFF_V_UV1_7_REG (SOC_ISP_YUVSC12P_REG_BASE + 0x15C) /* vertical uv coeff table. */

#endif // __ISP_YUVSC12P_REG_REG_OFFSET_H__
